The present invention relates generally to interrupt control; and, more particularly, it relates to scaleable interrupt control circuitry that performs arbitration and prioritization of any number of interrupt sources.
Many conventional computing systems necessarily need to accommodate increasing numbers of interrupt requests as such computing systems continue to grow in size and complexity. The conventional computing systems that perform arbitration and prioritization of these interrupt requests are commonly not expandable to include larger numbers of interrupt requests. That is to say, to accommodate larger numbers of interrupt requests for a given architecture, a real estate-design of the architecture is often necessitated as the traditional architectures cannot easily include larger numbers of sources. A re-design of the architecture of the circuitry is necessarily performed each time the number of sources feeding the interrupt circuitry changes. This inability for expansion presents many undesirable features. For example, whenever a system is being considered for re-design and the number of sources that perform interrupt changes (either increases or decreases), then there necessarily needs to be a re-design not only of the system itself, but also of the interrupt control circuitry. This is expensive in terms of engineer design time, and it substantially lengthens the turn-around time that is required to get a newly designed system to fabrication.
Another problem that arises in the design of interrupt circuitry is the calculation and control of propagation time through the arbitration logic circuitry. Not only can there be significant design time associated with simply accommodating varying numbers of interrupt sources, but there is necessarily a characterization and modeling challenge in accommodating the new number of interrupt sources as the propagation time required by the arbitration logic circuitry will intrinsically be modified as well. As traditional interrupt technology commonly employs a single gate for each interrupt source, when there is an increase in the number of interrupts, there will subsequently be an increase in the number of gates in the system given the one-to-one relationship between interrupt source and gate. It necessarily follows that there will similarly be an increase in the propagation time through the system, specifically through the arbitration logic circuitry.
Moreover, even conventional interrupt processing circuitry causes reprogrammable prioritization problems when the number of interrupt sources changes. For example, a number of clock cycles are typically required to perform the reprogramming of the prioritization when there has been a modification in the number of interrupt sources within conventional systems. Oftentimes, this relatively slow reprogramming prohibits the use of systems requiring a large number of interrupt sources in certain applications where speed of operation is an important design criterion. As many embedded applications are increasing the number of interrupt sources from the historical number of 32 to 64, there is great difficulty in accommodating this increased number across a broad range of products and product lines without expending significant amounts of time and energy in performing re-design of the interrupt control circuitry and its associated arbitration logic circuitry.
Further limitations and disadvantages of conventional and traditional systems will become apparent to one of skill in the art through comparison of such systems with the present invention as set forth in the remainder of the present application with reference to the drawings.